| Interface |
Interface Type |
MIPI-DSI (Display Serial Interface) |
dsi->mode_flags |
Uses DSI video interface |
|
Lane Count |
4 lanes |
dsi->lanes = 4; |
High-speed quad-lane |
|
DSI Mode |
Video mode (sync pulse) |
MIPI_DSI_MODE_VIDEO |
MIPI_DSI_MODE_VIDEO_SYNC_PULSE` |
|
Pixel Format |
RGB888 (24-bit) |
dsi->format = MIPI_DSI_FMT_RGB888; |
Each pixel = 3 bytes |
|
Color Order |
RGB |
DCS MADCTL (0x36, 0x00) |
No color inversion |
| Resolution & Timing |
Active Area |
1440 × 1600 |
get_modes() |
Portrait orientation |
|
Refresh Rate |
60 Hz |
Mode calculation |
Supported nominal rate |
|
Horizontal Porch |
HFP = 32, HSYNC = 16, HBP = 48 |
htotal math |
Pixels |
|
Vertical Porch |
VFP = 8, VSYNC = 4, VBP = 16 |
vtotal math |
Lines |
|
Pixel Clock |
≈ 158 MHz |
m->clock = … |
1440×1600×60 Hz total |
| Power & Reset |
Power Supply |
VDDI = 1.8 V, AVDD = 5.8 V, AVEE = –5.8 V |
Regulator/DT |
Analog + logic |
|
Reset Polarity |
Active Low |
GPIO_ACTIVE_LOW |
Hold ≥ 10 ms |
|
Reset Timing |
Assert > 10 ms → Deassert → Wait 120 ms |
prepare() |
From power-on seq |
|
Backlight |
PWM input |
pwm-backlight DT node |
100–200 Hz typical |
| Initialization Sequence |
Sleep-Out |
0x11 (wait ≥ 120 ms) |
vs035_prepare() |
Mandatory |
|
Set Pixel Format |
0x3A, 0x77 (RGB888) |
vs035_prepare() |
|
|
Memory Access Ctrl |
0x36, 0x00 (RGB, normal) |
vs035_prepare() |
|
|
Display On |
0x29 (wait 20 ms) |
vs035_prepare() |
|
|
Optional Vendor Regs |
Several 0xBA, 0xC0–0xC3 commands |
vs035_prepare() |
From init code table |
|
Display Off / Sleep In |
0x28, 0x10 |
unprepare() |
Power-down seq |
| Device Tree Overlay |
DSI Controller |
&dsi1 |
Overlay target |
Use correct port |
|
Reset GPIO |
<&gpio 17 GPIO_ACTIVE_LOW> |
reset-gpios |
From Pi header |
|
Backlight PWM |
<&pwm 0 0> |
backlight = <&bl> |
Optional simple node |
| Electrical |
Logic I/O Voltage |
1.8 V |
Supply spec |
Matches Pi DSI |
|
Max Frame Rate |
90 Hz (optional) |
Timing extension |
Overclock possible |